The present invention generally relates to delay chains, and more particularly to variable-length delay chains, digitally controlled oscillators, and programmable delay elements.
Digital techniques are widely used to synthesize clock signals. In a typical system, a digital clock synthesis unit (DCSU) includes a phase detector, filter, digitally-controlled oscillator (DCO), and divider arranged in a feedback loop. The phase detector compares the divided frequency of the DCO to a reference signal and transforms the phase or frequency difference into an error signal. The error signal is filtered and delivered to the DCO. The DCO responds to the filtered error signal by advancing or retarding the phase of the output signal. In this way, the DCSU tracks changes in the reference signal.
Unlike analog oscillators, DCOs use a digital input and can therefore assume only a finite number of oscillation frequencies. This means a DCO can never really produce an output clock which is perfectly synchronized with its reference; instead, it can only approximate such a clock by chattering back and forth between two adjacent frequencies bounding the target frequency. This process creates jitter or phase noise on the synthesized clock analogous to quantization noise in DACs (digital-to-analog converters) and ADCs (analog-to-digital converters).
The magnitude of the jitter, or the peak phase error, depends directly on the granularity of the frequency steps of the DCO and on the rate of change between two adjacent frequencies. In other words, a DCO with finer frequency steps and higher input control change rate will introduce less jitter on the output clock. Conventional digital clock synthesis units can produce relatively large delay steps and correspondingly large amounts of phase noise which may be unsuitable for many applications. There is thus a need in the art for improvements in the area of digital clock synthesis.